The present invention relates generally to data communications within a computer system. More specifically, the present invention relates to a differential receiver of a bus line.
Within a computer system, it is often desirable to connect a variety of peripherals to the system bus of the computer itself for communication with the central processing unit and other devices connected to the computer. A variety of bus types may be used, and for any bus it is important to have bus drivers and bus receivers that allow devices to communicate quickly, efficiently and accurately.
FIG. 1 illustrates an embodiment of a computer system 10. Computer system 10 includes a computer 12, a disk drive 14, a tape drive 16, and any number of other peripherals 18 such as card reader units, voice input/output, displays, video input/output, scanners, etc. The computer and peripherals in this example are connected via a Small Computer System Interface (SCSI) bus 20, although a wide variety of other buses may also be used.
Any number of computers or hosts may be present in computer system 10 and be connected to SCSI bus 20. Each computer may also contain a variety of hardware and software. By way of example, computer 12 includes a monitor 30, a motherboard 32, a wide variety of processing hardware and software 34 and a SCSI host adapter card (or interface card) 36. Host adapter card 36 provides an interface between the microcomputer bus of computer 12 located on motherboard 32 and SCSI bus 20.
SCSI is a universal parallel interface standard for connecting disks and other high performance peripherals to microcomputers. However, it should be appreciated that computer system 10 is an example of a system, and other interface standards having characteristics similar to SCSI may also be used in such a computer system. By way of example, an Intelligent Peripheral Interface (IPI) standard is one such other standard.
In one embodiment, SCSI bus 20 is an 8-bit parallel flat cable interface (18 total signals) with hand shakes and protocols for handling multiple hosts and multiple peripherals. It has both a synchronous and an asynchronous mode, and has defined software protocols. In the embodiment shown, the SCSI bus uses differential drivers, although SCSI is also available with single wire drivers. SCSI interface cards (such as card 36) plug into most microcomputer buses including VME, Multibus I and II, PCI, ISA, VL, EISA and MCA. In another embodiment, SCSI bus 20 is a 16-bit parallel cable interface (27 total signals). In other embodiments motherboard 32 has SCSI adapter card 36 incorporated into the motherboard itself, and a separate, plug-in adapter card is not needed. SCSI bus 20 is a multi-drop bus typically produced as a flat cable that connects from a computer 12 to any number of peripherals. In this example, disk drive 14, tape drive 16, and other peripherals 18 connect to SCSI bus 20 by tapping into the bus. In other examples, it is possible for any number of peripherals to be inside computer 12 in which case SCSI bus 20 may also be present inside computer 12 also.
Disk drive 14 includes the physical disk drive unit 40 and SCSI controller card 42 and other internal cables and device level interfaces (not shown) for enabling the unit to communicate with computer 12. After connecting to disk drive 14, SCSI bus 20 continues on to connect to tape drive 16. Tape drive 16 includes the physical tape drive 50, SCSI controller card 52, and other internal cables and interfaces (not shown) for communicating with computer 12.
SCSI bus 20 also connects to any number of other peripherals 18. In alternative embodiments of the invention, any of the peripherals shown may eliminate the SCSI controller card by using an xe2x80x9cembedded SCSIxe2x80x9d architecture in which the SCSI bus becomes also the device level interface. In these peripherals, a cable such as SCSI bus 20 may be connected directly from motherboard 32 of a computer to a peripheral without the need for connecting to an internal controller card.
FIG. 2 shows in greater detail 50 SCSI bus 20 and connections to it from computer 12 and a peripheral 18. SCSI bus 20 may come in a variety of standards. Illustrated here by way of example, is a 16-bit SCSI bus with a variety of its control signals shown. Shown are the signals data[0] 52 through data[15] 54, parity 56, ACK (acknowledge) 58, REQ (request) 60, and a variety of other control signals 62.
This example illustrates how one value from computer 12 may be transferred via SCSI bus 20 to peripheral 18. It should be appreciated that any number of data or control signals may be transferred back and forth on the SCSI bus. For example, computer 12 has a value 70 that passes through a driver 72 and over an electrical connection 74 to the bus line data[15]. At the peripheral end, the signal on bus line data[15] is passed by way of an electrical connection 76 to a receiver 78 whereby value 70 is received in peripheral 18. Techniques by which a value may be transmitted by a driver over a SCSI bus to be received by a receiver in another electronic device are well known to those of skill in the art.
FIG. 3 shows in greater detail a proposed apparatus 80 by which value 70 is transmitted from computer 12 to peripheral 18. FIG. 3 illustrates a proposed SCSI standard known as the ULTRA 2 Specification being proposed by the SPI-2 working group. As in FIG. 2, FIG. 3 shows a value 70 being transmitted by a driver 72 from computer 12 to a receiver 78 in peripheral 18. Because SCSI bus 20 uses a voltage differential technique of transferring information, value 70 is transmitted using a signal line 82 from driver 72 and also using its complement, signal/84. In other words, signal lines 82 and 84 are used to transmit information for bus line data[15] 54. In a similar fashion, information for other bus lines is transmitted using two signal lines.
The SCSI bus also uses a bias voltage in the termination at each end of the SCSI bus. The termination bias voltage is used during the arbitration phase of SCSI protocol in order to help determine which devices are asserting which bits on the bus. Without a termination bias voltage, it would be difficult to determine which device is asserting a data bit because bits not being asserted would be floating. The need for a termination bias voltage on a SCSI bus and its ramifications are discussed in greater detail below. To achieve the termination bias voltage, computer 12 includes a voltage source V(A) 86 (for example, 1.5 volts) and a voltage source V(B) 88 (for example, 1.0 volt) which are connected in series using resistors 90 (for example, 270 ohms), resistor 92 (for example, 138 ohms), and resistor 94 (for example, 270 ohms). This termination bias voltage circuit is connected to signal lines 82 and 84 as shown. Thus, point 91 is typically at 1.3 volts due to the termination bias voltage, and point 93 is typically at 1.2 volts due to the termination bias voltage. The termination bias voltage also results in an approximate termination resistance of 110 ohms.
In a similar fashion, peripheral 18 also includes a termination bias voltage. As in computer 12, resistors 95, 96, and 97 connect in series voltages V(A) and V(B). These voltages and resistances may have similar values as for computer 12 and are connected to signal lines 82 and 84 as shown. Also shown in FIG. 3 are multiple bus taps 98 symbolizing the variety of other devices, computers, and peripherals that may also tap onto SCSI bus 50.
This proposed technique for transmitting data over a SCSI bus uses a low-voltage swing differential (LVD) driver and a low offset voltage, high-speed, differential input receiver. The driver for this type of SCSI bus uses an asymmetrical output, where one direction has more drive strength than the other. The reason for this asymmetrical output is because of the termination bias voltage as shown in FIG. 3.
Unfortunately, this termination bias voltage and the asymmetrical driver output that it necessitates can have undesirable effects. The reason for the need for a termination bias voltage has to do with the dual use of the data lines of a SCSI bus. A SCSI bus includes data lines that are used during a data phase of communication, i.e., high-speed transmission of data. A SCSI bus also includes various control lines that are used to transmit control signals at a lower speed during a protocol phase of communication on the bus. However, the data lines of a SCSI bus have a dual use. During the protocol phase of communication, the data lines are also used to transmit control signals used for arbitration on the bus. Thus, the data lines of a SCSI bus must be able to operate in a high-speed data phase and also in a low-speed protocol phase. Operation of these lines in the protocol phase requires a termination bias voltage.
The data lines have this dual use because of the way peripherals indicate when they wish to use the SCSI bus. When a peripheral on a SCSI bus wishes to use the bus, it asserts one of the data lines. Each peripheral on the bus is associated with one of the data lines, thus it can be determined which peripheral wants to use the bus by which data line is being asserted. However, when one peripheral is asserting one data line, the other data signals must be driven to a known state so that the SCSI bus and its attached devices can determine which data line is being asserted. In other words, if the data lines are simply floated it would be difficult to determine which of many data lines is being asserted.
Therefore, pull-up voltages are used at each end of the SCSI bus so that any non-driven data lines are put into a negated state. Thus, when one peripheral asserts one data line, all of the other data lines will be in a negated state and it may then be determined which peripheral wishes to use the bus. These pull-up voltages are called termination bias voltages and are due to the dual use of the data lines of a SCSI bus. A termination bias voltage is present at each end of a SCSI bus and is used with single-ended drivers and also with differential drivers. Because of the termination bias voltages on a SCSI bus, the drivers must be asymmetrical, as will now be explained.
The need for an asymmetrical driver when a termination bias voltage is present may be seen by referring to FIG. 3. As described above, a termination bias voltage produces a difference of about 100 mV between the two signal lines 82 and 84. Thus, in order to achieve a 500 mV voltage swing for negating a signal, only 400 mV need be driven because of the 100 mV difference already present. However, when asserting a signal, the driver must drive 600 mV in order to achieve a 500 mV voltage swing in order to overcome the already present 100 mV. Thus, a driver must drive asymmetrically in order to negate or assert a signal when a termination bias voltage is present.
Asymmetrical drivers produce a number of problems. For one, the drivers must match the termination bias voltage which may be inaccurate. For example, if voltage source V(A) or any of resistors 95, 96 or 97 are out of tolerance, then there may not be exactly 100 mV differential between signals 82 and 84. A driver expecting an exact termination bias voltage of 100 mV may experience problems when driving asymmetrically if a particular expected termination bias voltage is out of tolerance. A symmetrical driver is thus desirable because there is no termination bias voltage, and thus, no such mismatch problems. Additionally, data can be transmitted at much higher speeds if symmetrical drivers are used. Furthermore, a symmetrical driver achieves a better signal to noise ratio. Therefore, because of the nature of a SCSI bus, the asymmetrical drivers used often cause difficulties. Of course, other buses using asymmetrical drivers for a variety of reasons may also experience the drawbacks associated with these drivers. The IEEE standard 1394 attempts to solve some of these problems, but does so only for a serial interface. IEEE-1394 is the industry-standard implementation of Apple Computer, Inc.""s FIREWIRE digital I/O system.
Another problem associated with a SCSI bus is the use of high-voltage differential drivers. A high-voltage driver may have a voltage differential of about 2.5 volts minimum, whereas a low-voltage differential driver may have a differential from about 260 mV to 780 mV. Because of the higher power required with a high-voltage driver, power dissipation is an issue and two or three integrated circuits may be needed to implement a SCSI interface. In other words, not all of the bus signals can be implemented on one chip because of power concerns, so more chips are needed to help dissipate the power. Unfortunately, the use of more than one chip to implement a SCSI interface leads to mismatch and timing skew between the chips. On the other hand, the use of low-voltage differential drivers saves power and allows all drivers and/or receivers for a SCSI bus to be integrated on one chip. Having all drivers or receivers on. one chip avoids mismatch and skew problems and is simpler to integrate into a greater circuit.
Therefore, it would be desirable to have a receiver apparatus for a bus that allows high-speed data transmission to occur using a symmetrical driver, yet still allow arbitration on a bus to occur in the standard fashion. It would also be desirable for such a receiver to have excellent signal to noise margins for transmitting data at high-speeds and to conserve power.
To achieve the foregoing, and in accordance with the purpose of the present invention, a low-voltage differential dual receiver for a bus is proposed that allows for symmetrical drivers by doing without a termination bias voltage. A high-speed receiver is used when transmitting data at high-speeds, and a lower performance, low-speed receiver is used for other bus phases.
The present invention separates the data phase and protocol phase of bus communication by using two receivers and optimizing each receiver for its particular function. The dual receiver includes a high-speed symmetrical receiver providing a high-speed symmetrical data path during the data phase of communication, and a low-speed receiver for the protocol phase having a built-in offset. The built-in offset allows the low-speed receiver to operate correctly during bus arbitration or SCAM. The built-in offset in the low-speed receiver takes the place of the termination bias voltage present in an asymmetrical bus. Incorporation of the built-in offset in the low-speed receiver allows the high-speed receiver to be driven symmetrically at higher speeds.
In a first embodiment of the built-in offset, a generation circuit produces a bulk voltage for one transistor of the differential transistor pair that is different than a supply voltage supplied to the bulk of the other transistor. In a second embodiment, each of the transistors of the pair is implanted with a different dosage to change the threshold voltage for each. In a third embodiment, resistors of different sizes are attached to the source of each transistor in the pair in order to produce a different voltage at each source. In a fourth embodiment, two replica comparators are used to monitor an offset voltage of the differential receiver and to send control signals to an adjustable current source. The current source is adjusted by having an up-down counter switch on and off various legs of the current source.
Advantageously, the high-speed and low-speed bus phases are separated so that a user can have the best of both worlds. Because the termination bias voltage is eliminated from the bus, data transmission may take place at high-speed using a symmetrical driver communicating with the high-speed receiver. This high-speed communication takes place without the drawbacks of asymmetrical communication. The low-speed receiver then handles the protocol phase of bus communication where a built-in offset is needed. This built-in offset may be implemented in a variety of ways depending upon integrated circuit process and design constraints. Additionally, use of a low-voltage differential driver allows a complete bus interface (including drivers and receivers for each bus line) to be integrated onto one chip, thus reducing mismatch and skew problems and saving power.
Additionally, by separating the data and protocol phases into two receivers, a more workable design results. A separate symmetrical high-speed data receiver is simpler to design and does not need an internal offset. Although a single receiver with a built-in offset could be used for both data and protocol communication, it is extremely difficult to design such a receiver to also operate at high speed for data communication. It is simpler to design one receiver with a built-in offset for operation at low speed in a protocol phase, and another receiver for operation at high speed in a data phase. Thus, having two separate receivers results in a simpler design that still achieves a purpose of allowing for high-speed symmetrical data communication.